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this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. september 2012 doc id 023354 rev 1 1/17 17 STL45N65M5 n-channel 650 v, 0.075 typ., 22.5 a mdmesh? v power mosfet in powerflat? 8x8 hv package datasheet ? preliminary data features 100% avalanche tested low input capacitance and gate charge low gate input resistance applications switching applications description this device is an n-channel mdmesh? v power mosfet based on an innovative proprietary vertical process technology, which is combined with stmicroelectronics? well-known powermesh? horizontal layout structure. the resulting product has extremely low on- resistance, which is unmatched among silicon- based power mosfets, making it especially suitable for applications which require superior power density and outstanding efficiency. figure 1. internal schematic diagram order code v dss @ t jmax r ds(on) max i d STL45N65M5 710 v < 0.086 22.5 a (1) 1. the value is rated according to r thj-case and limited by package. 3 3 3 ' $ 0ower&,!4?x(6 "ottomview !-v $ ' 3 table 1. device summary order code marking package packaging STL45N65M5 45n65m5 powerflat? 8x8 hv tape and reel www.st.com
contents STL45N65M5 2/17 doc id 023354 rev 1 contents 1 electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
STL45N65M5 electrical ratings doc id 023354 rev 1 3/17 1 electrical ratings table 2. absolute maximum ratings symbol parameter value unit v ds drain-source voltage 650 v v gs gate-source voltage 25 v i d (1) 1. the value is rated according to r thj-case and limited by package. drain current (continuous) at t c = 25 c 22.5 a i d (1) drain current (continuous) at t c = 100 c 18 a i dm (1),(2) 2. pulse width limited by safe operating area. drain current (pulsed) 90 a i d (3) 3. when mounted on fr-4 board of inch2, 2oz cu. drain current (continuous) at t amb = 25 c 3.8 a i d (3) drain current (continuous) at t amb = 100 c 2.4 a p tot (3) total dissipation at t amb = 25 c 2.8 w p tot (1) total dissipation at t c = 25 c 160 w i ar avalanche current, repetitive or not- repetitive (pulse width limited by t j max) 9a e as single pulse avalanche energy (starting t j = 25 c, i d = i ar , v dd = 50 v) 810 mj dv/dt (4) 4. i sd 22.5 a, di/dt 400 a/s, v dd = 400 v, v ds(peak) < v (br)dss. peak diode recovery voltage slope 15 v/ns t stg storage temperature - 55 to 150 c t j max. operating junction temperature 150 c table 3. thermal data symbol parameter value unit r thj-case thermal resistance junction-case max 0.78 c/w r thj-amb (1) 1. when mounted on fr-4 board of inch2, 2oz cu. thermal resistance junction-ambient max 45 c/w
electrical characteristics STL45N65M5 4/17 doc id 023354 rev 1 2 electrical characteristics (t c = 25 c unless otherwise specified) table 4. on /off states symbol parameter test conditions min. typ. max. unit v (br)dss drain-source breakdown voltage i d = 1 ma, v gs = 0 650 v i dss zero gate voltage drain current (v gs = 0) v ds = 650 v v ds = 650 v, t c =125 c 1 100 a a i gss gate-body leakage current (v ds = 0) v gs = 25 v 100 na v gs(th) gate threshold voltage v ds = v gs , i d = 250 a 3 4 5 v r ds(on) static drain-source on- resistance v gs = 10 v, i d = 14.5 a 0.075 0.086 table 5. dynamic symbol parameter test conditions min. typ. max. unit c iss c oss c rss input capacitance output capacitance reverse transfer capacitance v ds = 100 v, f = 1 mhz, v gs = 0 - 3470 82 7 - pf pf pf c o(er) (1) 1. energy related is defined as a constant equival ent capacitance giving the same stored energy as c oss when v ds increases from 0 to 80% v dss equivalent output capacitance energy related v gs = 0, v ds = 0 to 80% v (br)dss -79-pf c o(tr) (2) 2. time related is defined as a constant equivalent capacitance giving the same charging time as c oss when v ds increases from 0 to 80% v dss equivalent output capacitance time related -280-pf r g intrinsic gate resistance f = 1 mhz open drain - 2 - q g q gs q gd total gate charge gate-source charge gate-drain charge v dd = 520 v, i d = 17.5 a, v gs = 10 v (see figure 16 ) - 82 18.5 35 - nc nc nc
STL45N65M5 electrical characteristics doc id 023354 rev 1 5/17 table 6. switching times symbol parameter test conditions min. typ. max. unit t d (v) t r (v) t f (i) t c (off) voltage delay time voltage rise time current fall time crossing time v dd = 400 v, i d = 22.5 a, r g = 4.7 , v gs = 10 v (see figure 20 ) - 79.5 11 9.3 16 - ns ns ns ns table 7. source drain diode symbol parameter test conditions min. typ. max. unit i sd (1) i sdm (1),(2) 1. the value is rated according to r thj-case and limited by package. 2. pulse width limited by safe operating area source-drain current source-drain current (pulsed) - 22.5 90 a a v sd (3) 3. pulsed: pulse duration = 300 s, duty cycle 1.5% forward on voltage i sd = 22.5 a, v gs = 0 - 1.5 v t rr q rr i rrm reverse recovery time reverse recovery charge reverse recovery current i sd = 22.5 a, di/dt= 100 a/s v dd = 100 v (see figure 17 ) - 346 6 35 ns c a t rr q rr i rrm reverse recovery time reverse recovery charge reverse recovery current i sd = 22.5 a, di/dt= 100 a/s v dd = 100 v, t j = 150 c (see figure 17 ) - 432 8.4 39 ns c a
electrical characteristics STL45N65M5 6/17 doc id 023354 rev 1 2.1 electrical characteristics (curves) figure 2. safe operating area figure 3. thermal impedance figure 4. output characteristics figure 5. transfer characteristics figure 6. gate charge vs gate-source voltage figure 7. static drain-source on-resistance i d 10 1 0.1 0.1 1 100 v d s (v) 10 (a) oper a tion in thi s a re a i s limited b y m a x r d s (on) 10 s 100 s 1m s 10m s tj=150c tc=25c s ingle p u l s e am14956v1 10 -5 10 -4 10 - 3 10 -2 t p ( s ) 10 -2 10 -1 k 0.2 0.05 0.02 0.01 0.1 s ingle p u l s e =0.5 zth powerflat 8 x 8 hv i d 60 40 20 0 0 10 v d s (v) 20 (a) 5 15 25 8 0 6v 7v v g s =10v am14957v1 i d 60 40 20 0 4 v g s (v) 8 (a) 3 6 9 8 0 5 7 v d s =25v am1495 8 v1 v g s 6 4 2 0 0 20 q g (nc) (v) 8 0 8 40 60 10 v dd =520v i d =17.5a 100 12 3 00 200 100 0 400 500 v d s v d s (v) am14960v1 r d s (on) 0.071 0.066 0 20 i d (a) ( ) 10 25 0.076 0.0 8 1 15 5 am14959v1
STL45N65M5 electrical characteristics doc id 023354 rev 1 7/17 figure 8. capacitance variations figure 9. output capacitance stored energy figure 10. normalized gate threshold voltage vs. temperature figure 11. normalized on-resistance vs. temperature figure 12. drain-source diode forward characteristics figure 13. normalized v ds vs. temperature c 1000 100 10 1 0.1 10 v d s (v) (pf) 1 10000 100 ci ss co ss cr ss am14961v1 e o ss 6 4 2 0 0 100 v d s (v) ( j) 400 8 200 3 00 10 12 500 600 14 16 am14962v1 v g s (th) 1.00 0.90 0. 8 0 0.70 -50 0 t j (c) (norm) -25 1.10 75 25 50 100 i d =250 a am05459v2 r d s (on) 1.7 1. 3 0.9 0.5 -50 0 t j (c) (norm) -25 75 25 50 100 0.7 1.1 1.5 1.9 2.1 v g s =10v i d =17.5v am05460v2 v s d 0 20 i s d (a) (v) 10 50 3 0 40 0 0.2 0.4 0.6 0. 8 1.0 1.2 t j =-50c t j =150c t j =25c am05461v1 v d s -50 0 t j (c) (norm) -25 75 25 50 100 0.92 0.94 0.96 0.9 8 1.00 1.04 1.06 1.02 i d = 1ma 1.0 8 am10 3 99v1
electrical characteristics STL45N65M5 8/17 doc id 023354 rev 1 figure 14. switching losses vs. gate resistance (1) 1. eon including reverse recovery of a sic diode e 3 00 200 100 0 0 20 r g ( ) ( j) 10 3 0 400 500 600 40 i d =2 3 a v dd =400v eon eoff v g s =10v am1496 3 v1
STL45N65M5 test circuits doc id 023354 rev 1 9/17 3 test circuits figure 15. switching times test circuit for resistive load figure 16. gate charge test circuit figure 17. test circuit for inductive load switching and diode recovery times figure 18. unclamped inductive load test circuit figure 19. unclamped inductive waveform figure 20. switching time waveform am0146 8 v1 v g s p w v d r g r l d.u.t. 2200 f 3 . 3 f v dd am01469v1 v dd 47k 1k 47k 2.7k 1k 12v v i =20v=v gmax 2200 f p w i g =con s t 100 100nf d.u.t. v g am01470v1 a d d.u.t. s b g 25 a a b b r g g fa s t diode d s l=100 h f 3 . 3 1000 f v dd am01471v1 v i p w v d i d d.u.t. l 2200 f 3 . 3 f v dd am01472v1 v (br)d ss v dd v dd v d i dm i d am05540v2 id vg s vd s 90 % vd s 10 % id 90 % vg s on tdel a y-off tf a ll tri s e tcro ss -over 10 % vd s 90 % id vg s (i(t)) on -off tf a ll tri s e - )) concept w a veform for ind u ctive lo a d t u rn-off
package mechanical data STL45N65M5 10/17 doc id 023354 rev 1 4 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com. ecopack is an st trademark.
STL45N65M5 package mechanical data doc id 023354 rev 1 11/17 table 8. powerflat? 8x8 hv mechanical data dim. mm min. typ. max. a 0.80 0.90 1.00 a1 0.00 0.02 0.05 b 0.95 1.00 1.05 d8.00 e8.00 d2 7.05 7.20 7.30 e2 4.15 4.30 4.40 e2.00 l 0.40 0.50 0.60 aaa 0.10 bbb 0.10 ccc 0.10
package mechanical data STL45N65M5 12/17 doc id 023354 rev 1 figure 21. powerflat? 8x8 hv drawing mechanical data index area top view plane seating 0.08 c bottom view side view pin#1 id d e b a e2 d2 l 0.40 0.20 0.008 c bbb c a b b a aaa c aaa c a1 ccc c 8 222 8 71_rev_b
STL45N65M5 package mechanical data doc id 023354 rev 1 13/17 figure 22. powerflat? 8x8 hv recommended footprint 7.30 1.05 2.00 7.70 4.40 0.60 footprint
packaging mechanical data STL45N65M5 14/17 doc id 023354 rev 1 5 packaging mechanical data figure 23. powerflat? 8x8 hv tape figure 24. powerflat? 8x8 hv package orientation in carrier tape. w (16.000. 3 ) e (1.750.1) f (7.500.1) a0 ( 8 . 3 00.1) p1 (12.000.1) p2 (2.00.1) p0 (4.00.1) d0 ( 1.550.05) d1 ( 1.5 min) t (0. 3 00.05) b0 ( 8 . 3 00.1) k0 (1.100.1) note: b as e a nd b u lk qua ntity 3 000 pc s 8 229 8 19_t a pe_reva
STL45N65M5 packaging mechanical data doc id 023354 rev 1 15/17 figure 25. powerflat? 8x8 hv reel 8 229 8 19_reel_reva
revision history STL45N65M5 16/17 doc id 023354 rev 1 6 revision history table 9. document revision history date revision changes 20-sep-2012 1 first release.
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